1. Field of the Invention
The present invention relates to a semiconductor memory which has dynamic memory cells and word lines connected to the memory cells, and supplies a voltage higher than a power supply voltage to the word lines in accessing the memory cells.
2. Description of the Related Art
Recently, semiconductor memories having dynamic memory cells (DRAMs or pseudo SRAMs) have been used for work memories to be mounted on portable equipment such as a cellular phone. Since DRAM memory cells are smaller than SRAM memory cells, the use of DRAMs allows a reduction in product cost. In the meantime, semiconductor memories to be mounted on portable equipment require low power consumption for the sake of extending operating time of the battery. With cellular phones in particular, lower standby currents are of importance in order to extend available standby time. DRAMs and pseudo SRAMs need to perform periodic refresh operations on their memory cells even while the portable equipment is not in operation, and these refresh operations contribute to increases in standby currents. Thus, various contrivances for reducing the standby current have been made to DRAMs and pseudo SRAMs.
For example, there has been proposed a technology in which the operation of a boost voltage generator for generating a boost voltage of word lines is stopped during a self-refresh mode, and the output node (boost node) of the boost voltage generator is fixed to an external supply voltage (disclosed in for example, Japanese Unexamined Patent Application Publication No. Hei 7-287980; hereinafter, referred to as Reference 1). There has also been proposed a technology in which the operation of the boost voltage generator is stopped for a predetermined period after the completion of a refresh operation (a concentrated refresh operation during a self-refresh mode), and the word lines are grounded in this period (disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2003-77273; hereinafter, referred to as Reference 2).
Now, in semiconductor memories having dynamic memory cells, the selection voltage of the word lines is set to a boost voltage higher than the power supply voltage so that the charges of data retained in the memory cells is made greater for improving read margins. Transistors supplied with the boost voltage at their gates are likely to have gate induced drain leakage (GIDL) currents. Since the GIDL currents flow between the drains and substrates of the transistors or between the sources and substrates of the same depending on the gate voltages, they increase as the gate voltages increase. In the semiconductor memories of this type, serious problems have thus occurred due to GIDL-based increases in the standby currents of transistors inside word drivers especially if the transistors receive the boost voltage at their gates. In particular, in the case of pMOS transistors that receive the boost voltage at their gates, the boost voltage is supplied to the substrates (wells). This increases the voltage differences between the drains and the substrates or the voltage differences between the sources and the substrates, causing greater GIDL currents easily.
For instance, a pMOS transistor under a gate voltage (boost voltage) of 3.2 V produces a GIDL current per gate width (for example, 1×10−11 A/μm) which is approximately 50 times larger than the GIDL current under a gate voltage (power supply voltage) of 1.8 V (for example, 2×10−13 A/μm). Assuming a pseudo SRAM in which the pMOS transistors in the word drivers receive the boost voltage (3.2 V) at their gates and have a total gate width of approximately 1×106 μm, the GIDL currents of these pMOS transistors sum up to approximately 10 μA.
In addition, GIDL lowers the substrate voltage (boost voltage) of the pMOS transistors. Thus, the boost voltage generator for generating the boost voltage must operate to compensate for the falling-down in voltage. In general, boost voltage generators generate boost voltages by pumping up their coupling capacitors. In a boost voltage generator in single-stage configuration for generating the boost voltage with a single coupling capacitor, the generation efficiency of the boost voltage is on the order of 40–50%. In a boost voltage generator in two-stage configuration for generating the boost voltage with two coupling capacitors, the generation efficiency of the boost voltage is on the order of 20–25%. Recently, the external supply voltage has been decreasing because of transistor miniaturization, and semiconductor memories implementing boost voltage generators of two-stage configuration are on the increase. Assuming that the boost voltage generators of two-stage configuration have an efficiency of generation of 20%, GIDL of 10 μA must be compensated by consuming five times as much current, or 50 μA. Since typical DRAMs have a specification of 100–200 μA in standby current, the effect of GIDL on the standby current is not negligible.
Meanwhile, setting nMOS transistors to a negative substrate voltage requires a negative voltage generator. The efficiency of generation thereof is on the order of 75–80%, however. Consequently, the amount of an increase in current consumption ascribable to GIDL occurring in the nMOS transistors is smaller than that of an increase in current consumption ascribable to GIDL occurring in the pMOS transistors.
There has been no conventional technology for avoiding the occurrence of GIDL in the transistors receiving a boost voltage at their gates in a semiconductor memory that has dynamic memory cells and is supplied with the boost voltage for word lines.
In the foregoing Reference 1, the boost voltage generator stops during the self-refresh mode, and the voltage of the supply line of the boost voltage is forcefully set at the power supply voltage. In performing a refresh operation, it is thus necessary to postpone the operation of selecting the word lines until the boost voltage comes to a predetermined voltage. This means deterioration in performance of the pseudo SRAM. Besides, the next memory access after the stop of the boost voltage generator has to start after the boost voltage generator restarts operation and the boost voltage rises to a predetermined value. As a result, if the Reference 1 is applied to a pseudo SRAM in which a conflict can occur between access requests (read request and write request) and a refresh request, it takes a long time to make the first access after a refresh. This leads to deterioration in performance of the pseudo SRAM since the access time in the product specification has to be set to the worst value.
The foregoing Reference 2 is applicable only during the self-refresh mode for performing a concentrated refresh operation. For example, if the Reference 2 is applied to a DRAM which performs distributed refresh operations during the self-refresh mode, the standby current cannot be reduced satisfactorily due to a decrease in the stop period of the boost voltage generator and an increase in the frequency of stops and restarts thereof. Moreover, if the Reference 2 is applied to a pseudo SRAM in which a conflict can occur between memory access requests and a refresh request, and to a DRAM in which refresh requests are supplied from exterior at arbitrary timing, it takes a long time to make the first memory access after a refresh as with the Reference 1.